_______________general description the max1160 10-bit, monolithic analog-to-digital con- verter (adc) is capable of 20msps minimum word rates. an on-board track/hold ensures excellent dynam- ic performance without the need for external compo- nents. a 5pf input capacitance minimizes drive requirement problems. inputs and outputs are ttl compatible. an overrange output is provided to indicate overflow conditions. output data format is straight binary. power dissipation is low at only 1w with +5v and -5.2v power-supply voltages. the max1160 also accepts wide ?v input voltages. the max1160 is available in 28-pin dip and so pack- ages in the commercial temperature range. ________________________applications medical imaging professional video radar receivers instrumentation digital communications ____________________________features ? monolithic 20msps converter ? on-chip track/hold ? bipolar, ?v analog input ? 60db snr at 1mhz input ? 5pf input capacitance ? ttl outputs max1160 10-bit, 20msps, ttl-output adc ________________________________________________________________ maxim integrated products 1 coarse adc t/h amplifier bank successive interpolation stage i successive interpolation stage i + 1 successive interpolation stage n analog prescaler analog input 4 10 digital output decoding network . . . . ________________functional diagram 19-1189; rev 0; 3/97 for the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 part max1160acpi MAX1160BCPI max1160acwi 0? to +70? 0? to +70? 0? to +70? temp. range pin-package 28 wide plastic dip 28 wide plastic dip 28 so max1160bcwi 0? to +70? 28 so ______________ordering information evaluation kit available __________________pin configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dip/so dv cc v ee agnd v cc vfb vsb vrm vin vst vft v cc agnd v ee clk dgnd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 dgnd dv cc max1160 top view top view
max1160 10-bit, 20msps, ttl-output adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5.0v, v ee = -5.2v, dv cc = +5.0v, v in = 2.0v, vsb = -2.0v, vst = +2.0v, f clk = 20mhz, 50% clock duty cycle, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc .......................................................................................................... 6v v ee ......................................................................................................... -6v analog input ...................................................... vfb vin vft vft, vfb ........................................................................... 3v, -3v reference-ladder current .................................................. 12ma clk input ............................................................................... v cc digital outputs ..................................................... 30ma to -30ma continuous power dissipation (t a = +70 c) plastic dip ...................................................................... 1.14w so ....................................................................................... 1w operating temperature range ............................... 0 c to +70 c junction temperature ..................................................... +150 c storage temperature range ............................. -65 c to +150 c lead temperature (soldering, 10sec). ............................ +300 c v v v i vi v i vi v vi vi vi v vi vi v vi test level ns 20 t a = +25 c acquisition time ps-rms 5 t a = +25 c aperture jitter time ns 14 18 t a = +25 c output delay clock cycle 1 pipeline delay (latency) ns 20 overvoltage recovery time mhz 20 maximum conversion rate / c 0.8 reference-ladder tempco 500 800 reference-ladder resistance mhz 120 3db small signal input bandwidth pf 5 input capacitance k 75 300 t a = -55 c to +125 c input resistance lsb 0.5 differential nonlinearity lsb 1.0 bits 10 resolution integral nonlinearity k 100 300 input resistance a 75 t a = -55 c to +125 c input bias current a 30 60 v in = 0v input bias current v 2.0 input voltage range guaranteed no missing codes units max1160a min typ max conditions parameter 20 5 14 18 1 20 20 0.8 500 800 120 5 75 300 0.75 1.5 10 100 300 75 30 60 2.0 guaranteed max1160b min typ max v lsb 2.0 positive full-scale error 2.0 v lsb 2.0 negative full-scale error 2.0 v ns 1 t a = +25 c aperture delay time 1 dc accuracy ( full scale, 250khz sample rate, t a = +25 c) analog input reference input timing characteristics
max1160 10-bit, 20msps, ttl-output adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +5.0v, v ee = -5.2v, dv cc = +5.0v, v in = 2.0v, vsb = -2.0v, vst = +2.0v, f clk = 20mhz, 50% clock duty cycle, t a = t min to t max , unless otherwise noted.) t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 1mhz 54 57 52 55 55 58 iv 57 60 i f in = 10mhz f in = 3.58mhz f in = 1mhz max1160b min typ max 8.7 8.3 7.0 effective number of bits (enob) 7.5 bits parameter conditions max1160a min typ max units 9.2 8.8 test level t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 3.58mhz 53 55 51 53 54 56 iv 56 58 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 10mhz 47 49 44 46 signal-to-noise ratio (without harmonics) (snr) 47 50 db iv 50 53 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 1mhz 54 57 51 54 54 57 iv 57 60 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 3.58mhz 53 55 50 52 53 55 iv 56 58 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 10mhz 43 45 42 44 total harmonic distortion (thd) 45 47 db iv 46 48 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 1mhz 52 54 49 52 iv 55 57 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 3.58mhz 51 52 48 51 iv 54 55 i t a = +25 c t a = 0 c to +70 c, t a = -25 c to +85 c f in = 10mhz 41 44 40 signal-to-noise and distortion ratio (sinad) 43 iv 44 47 i f in = 1mhz 67 67 v db spurious-free dynamic range (sfdr) f in = 3.58mhz and 4.35mhz 0.5 v 0.7 % differential gain db t a = +25 c t a = +25 c f in = 3.58mhz and 4.35mhz 0.2 v 0.2 degrees differential phase t a = +25 c dynamic performance
max1160 10-bit, 20msps, ttl-output adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +5.0v, v ee = -5.2v, dv cc = +5.0v, v in = 2.0v, vsb = -2.0v, vst = +2.0v, f clk = 20mhz, 50% clock duty cycle, t a = t min to t max , unless otherwise noted.) v v 2.4 4.5 logic 1 voltage 2.4 4.0 iv a 0 5 20 t a = +25 c maximum input current low 0 5 20 v v 0.8 logic 0 voltage 0.8 pulse width high (clk) ns 20 300 iv 20 300 maximum input current high pulse width low (clk) a ns 20 iv 20 iv 0 5 20 0 5 20 t a = +25 c test level units max1160a min typ max conditions parameter max1160b min typ max logic 1 voltage v 2.4 iv 2.4 logic 0 voltage v 0.6 iv 0.6 4.75 5.0 5.25 iv 4.75 5.0 5.25 dv cc 4.75 5.25 iv 4.75 5.25 v cc power dissipation 1.0 1.3 vi 1.0 1.3 -4.95 -5.2 -5.45 iv -4.95 -5.2 -5.45 -v ee power-supply rejection v 1.0 v 1.0 v cc = 5v 0.25v, v ee = -5.2v 0.25v lsb w 40 55 vi 40 55 di cc 118 145 vi 118 145 i cc 40 57 vi 40 57 -i ee ma digital inputs digital outputs power-supply requirements currents voltages test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indicates the specific device testing actually per - formed during production and quality assurance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. unless otherwise noted, all tests are pulsed; therefore, t j = t c = t a . test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a = +25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. ______________________________________________________________ pin description name 1, 13 dgnd 2 d0 pin 12 d10 15 clk 3?0 function 16, 27 v ee digital ground d1?8 ttl output (lsb) ttl outputs 11 d9 ttl output (msb) 14, 28 dv cc +5v supply (digital) ttl output overrange clock -5.2v supply (analog) name 20 vst 19 pin vft 21 18, 25 v cc vin function 22 17, 26 agnd vrm 23 vsb sense for top of reference ladder 24 vfb force for top of reference ladder +5v supply (analog) analog input analog ground middle of voltage reference ladder sense for bottom of reference ladder force for bottom of reference ladder
max1160 10-bit, 20msps, ttl-output adc _______________________________________________________________________________________ 5 80 20 1 10 100 signal-to-noise ratio vs. input frequency 40 30 max1160-01 input frequency (mhz) snr (db) 60 50 70 f s = 20msps 80 20 1 10 100 signal-to-noise and distortion vs. input frequency 40 30 max1160-03 input frequency (mhz) sinad (db) 60 50 70 f s = 20msps 0 -120 0 7 10 8 9 1 2 3 4 5 6 spectral response -60 -90 max1160-05 input frequency (mhz) amplitude (db) -30 f s = 20msps f in = 1mhz 80 20 1 10 100 snr, thd, sinad vs. sample rate 40 30 max1160-04 sample rate (msps) snr, thd, sinad (db) 60 50 70 sinad snr, thd f in = 1mhz 65 40 -25 50 75 0 25 snr, thd, sinad vs. temperature 50 45 max1160-06 temperature (?) snr, thd, sinad (db) 60 55 sinad snr f s = 20msps f in = 1mhz thd thd snr __________________________________________ t ypical operating characteristics (t a = +25 c, unless otherwise noted.) 80 20 1 10 100 total harmonic distortion vs. input frequency 40 30 max1160-02 input frequency (mhz) thd (db) 60 50 70 f s = 20msps ______________ detailed description the max1160 requires few external components to achieve the stated operation and performance. figure 2 shows the typical interface requirements when using the max1160 in normal circuit operation. the following section provides a description of the pin functions, and outlines critical performance criteria to consider for achieving the optimal device performance. power supplies and grounding the max1160 requires -5.2v and +5v analog supply voltages. the +5v supply is common to analog v cc and digital d v cc . a ferrite bead in series with each supply line reduces the transient noise injected into the analog v cc . connect these beads as close to the device as possible. the connection between the beads and the max1160 should not be shared with any other device. bypass each power-supply pin as close to the device as possible. use 0.1 f for v ee and v cc , and 0.01 f for dv cc (chip capacitors are recommended).
the max1160 has two grounds: agnd and dgnd. these internal grounds are isolated on the device. use ground planes for optimum device performance. use dgnd for the dv cc return path (typically 40ma) and for the return path for all digital output logic interfaces. separate agnd and dgnd from each other, connect - ing them together only through a ferrite bead at the device. connect a schottky or hot carrier diode between agnd and v ee . the use of separate power supplies between v cc and dv cc is not recommended due to potential power-supply-sequencing latchup conditions. for opti - mum performance, use the recommended circuit shown in figure 2. voltage reference the max1160 requires the use of two voltage refer - ences: vft and vfb. vft is the force for the top of the voltage-reference ladder (typically +2.5v); vfb (typical - ly -2.5v) is the force for the bottom of the voltage-refer - ence ladder. both voltages are applied across an 800 internal reference-ladder resistance. the +2.5v voltage source for reference vft must be current limited to 20ma (max) if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. in addition, there are three reference-ladder taps (vst, vrm, and vsb). vst is the sense for the top of the reference ladder (+2v), vrm is the midpoint of the ladder (typically 0v), and vsb is the sense for the bottom of the reference ladder (-2v). the voltages at vst and vsb are the device? true full-scale input volt - ages when vft and vfb are driven to the recommend - ed voltages (typically +2.5v and -2.5v, respectively). these points should be used to monitor the device? actual full-scale input range. when not being used, a decoupling capacitor of 0.01 f (chip capacitor pre - ferred) connected to agnd from each tap is recom - mended to minimize high-frequency noise injection. figure 2 shows an example of a recommended refer - ence-driver circuit. ic1 is a max6225, a 2.5v reference with an accuracy of 0.2%. the 10k potentiometer r1 supports a minimum adjustable range of 0.6%. use an op07 or equivalent device for ic2. r2 and r3 must be matched to within 0.1% with good tc tracking to main - tain 0.3lsb matching between vft and vfb. if 0.1% matching is not met, then r4 can be used to adjust the vfb voltage to the desired level. adjust vft and vfb such that vst and vsb are exactly +2v and -2v, respectively. the analog input range scales proportionally with respect to the reference voltage if a different input range is required. the maximum scaling factor for device opera - tion is 20% of the recommended reference voltages of vft and vfb. however, because the device is laser trimmed to optimize performance with 2.5v references, its accuracy degrades if operated beyond a 2% range. max1160 10-bit, 20msps, ttl-output adc 6 _______________________________________________________________________________________ clk t pwh n - 2 n - 1 n data valid n data valid n + 1 t pwl t d n + 1 n + 2 output data figure 1a. timing diagram clk data valid t d output data figure 1b. single-event clock table 1. timing parameters description units t d clk to data valid propagation delay ns t pwh clk high pulse width ns parameter 20 300 t pwl clk low pulse width ns 20 min typ max 14 18
max1160 10-bit, 20msps, ttl-output adc _______________________________________________________________________________________ 7 coarse adc successive interpolation stage 1 successive interpolation stage n analog prescaler digital outputs decoding network v ee v ee agnd agnd v cc v cc dv cc dv cc dgnd dgnd fb fb fb +5v -5.2v +5v r1 10k r2 30k r3 30k r4 10k 1 m f 0.01 m f 0.01 m f 1 m f 10 m f 10 m f 1 m f c1 0.01 m f c2 0.01 m f c3 0.01 m f c4 0.01 m f c6 0.1 m f c7 0.1 m f c8 0.1 m f c9 0.1 m f c10 0.01 m f c11 0.01 m f c5 0.01 m f vin (?v) ?.5v max clk (ttl) vin vft vin clk vst vrm vsb vfb gnd vout vtrim r5 100 w 2.5v 1 3 2 4 6 7 8 r 2r 2r 2r 2r r d1 -5.2v = agnd +5v = dgnd d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 2 4 5 6 notes: 1) d1 = schottky or hot carrier diode 2) fb = ferrite bead, fair rite #2743001111 to be mounted as closely to the device as possible. the ferrite bead to adc connection should not be shared with any other device. 3) c1?11 = chip capacitor (recommended) mounted as close to device's pin as possible. 4) use of a separate supply for v cc and dv cc is not recommended. 5) r5 provides current limiting to 45ma. (overrange) (msb) (lsb) 4 -2.5v max1160 ic1 ic2 op07 max6225 figure 2. typical operating circuit the following errors are defined: +fs error = top of ladder offset voltage = ? (+fs - vst + 1lsb) -fs error = bottom of ladder offset voltage = ? (-fs - vsb - 1lsb) where the +fs (full-scale) input voltage is defined as the output transition between 11 1111 1110 and 11 1111 1111, and the -fs input voltage is defined as the output transi - tion between 00 0000 0000 and 00 0000 0001 (table 2). analog input vin is the analog input. the full-scale input range will be 80% of the reference voltage, or 2v with vfb = -2.5v and vft = +2.5v. the analog input? drive requirements are minimal when compared to conventional flash converters. this is due to the max1160? extremely low (5pf) input capacitance and very high (300k ) input resistance. for example, for an input signal of 2vp-p with a 10mhz input frequency, the peak output current required for the driving circuit is only 628 a. clock input the max1160 is driven from a single-ended ttl input (clk). the clk pulse width (t pwh ) must be kept between 20ns and 300ns to ensure proper operation of the internal track/hold amplifier (figure 1a). when oper - ating the max1160 at sampling rates above 3msps, it is recommended that the clock input duty cycle be kept at
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. max1160 10-bit, 20msps, ttl-output adc 50% to optimize performance, but performance will not be degraded if kept within the 40% to 60% range. the analog input signal is latched on the rising edge of clk. the clock input must be driven from fast ttl logic (vih 4.5v, t rise < 6ns). in the event the clock is dri - ven from a high current source, use a 100 resistor (r5) in series to limit current to approximately 45ma. digital outputs the format of the output data (d0?9) is straight binary (table 2). the outputs are latched on the rising edge of clk with a typical propagation delay of 14ns. there is a one-clock-cycle latency between clk and the valid output data (figure 1a). the digital outputs?rise and fall times are not symmetri - cal. typical propagation delay is 14ns for the rise time and 6ns for the fall time (figure 4). the nonsymmetri - cal rise and fall times create approximately 8ns of in- valid data. overrange output the overrange output (d10) is an indication that the analog input signal has exceeded the positive full-scale input voltage by 1lsb. when this condition occurs, d10 will switch to logic 1. all other data outputs (d0?9) will remain at logic 1 as long as d10 remains at logic 1. this feature makes it possible to include the max1160 in higher-resolution systems. evaluation board the max1160 ev kit is available to help designers demonstrate the max1160? full performance. this board includes a reference circuit, a clock-driver cir - cuit, output data latches, and an on-board reconstruc - tion of the digital data. a separate data sheet describing the operation of this board is also available. contact the factory for price and availability. vin vft v cc v ee analog prescaler figure 3. analog equivalent input circuit table 2. output data information clk in data out (actual) 2.4v 3.5v 2.4v 0.5v 0.8v t pd1 typ 6ns n n + 1 data out (equivalent) (n - 1) n (n - 1) n t rise 6ns (n - 2) (n - 2) 14ns typ invalid data invalid data invalid data invalid data figure 4. digital output characteristics analog input > +2v + 1/2lsb +2v - 1lsb 0v 0 0 1 overrange d10 output code d9?0 11 1111 1111 11 1111 111 -2v + 1lsb 0 00 0000 000 < 2v 0 00 0000 0000 ( indicates the flickering bit between logic 0 and 1.)
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